发明名称 VERIFICATION TECHNIQUE FOR LSI DEVELOPMENT
摘要 <P>PROBLEM TO BE SOLVED: To provide an efficient and effective verification technique for use in verifying a block whose operation and output signal vary depending on the timing and order of input signals. <P>SOLUTION: An input/output analysis test bench is provided which associates and integrates an input analysis test bench for analyzing the input signals and an output analysis test bench for analyzing the output signals. The input/output analysis test bench has a mechanism for verifying in real time the determination of inhibiting action upon detecting an expected output signal from the test bench analyzing the expected operation and input signal of the block to be verified. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004362096(A) 申请公布日期 2004.12.24
申请号 JP20030157541 申请日期 2003.06.03
申请人 CANON INC 发明人 MURAYAMA KOHEI
分类号 G06F12/16;G06F11/22 主分类号 G06F12/16
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