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发明名称
Latency control circuit in memory device using delay locked loop
摘要
申请公布号
KR100618797(B1)
申请公布日期
2006.09.08
申请号
KR20000005491
申请日期
2000.02.03
申请人
发明人
分类号
G11C8/00
主分类号
G11C8/00
代理机构
代理人
主权项
地址
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