| 摘要 |
Non-volatile memory transistors (51) have a semiconductor substrate (11) with spaced apart source (37) and drain (39) regions defining a channel, a layer of tunnel oxide 13) over the channel and a conductive layer of carbon nanotubes (31) over the tunnel oxide. In patterning, mesas (35) are formed retaining desired locations of nanotubes as floating gates. The mesas are used for self-aligned implantation of source and drain electrodes. The nanotubes, being deposited as a porous randomly arranged matted layer, allow for etch removal of the support layer so that the nanotubes rest directly on tunnel oxide. The nanotubes are protected with insulative material (55) and a conductive control gate (57) is placed over the nanotube floating gate layer.
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