| 摘要 |
A memory device for detecting a bit line leakage current is provided to reduce a test cost and improve an error detecting rate by measuring the leakage current of a plurality of bit lines. A memory cell is arranged in the cross point between a word line and a bit line of the memory cell array block(110). A data output path unit(120) includes circuit blocks(21,22,23,24) which amplify and buffer data of the global data line pair delivered from the local data line pair and generates the data output signal. A column decoder(130) generates a first column selection signal selecting the bit line by decoding the address signals provided from the outside. A bit line leakage current measuring unit(150) includes a first switch(50), a second switch(53), a resistance(54) and a measurement pad(55). The bit line leakage current measuring unit monitors the direct drain quiescent current flowing to the measurement line connected to the local data line pair in response to the test mode signal. A first memory apparatus(100) sets the word line to a disable state in the test mode measuring the leakage current of the bit line. A first switch connects the local data line pair to a first measurement line. The second switch connects the first measurement line to a second side gad line in response to the test mode signal. A resistance is connected between the power supply voltage and the second measurement line. The measurement pad is connected to the second measurement line.
|
