An Array Substrate Manufacturing Method, An Array Substrate And A Display Panel

摘要

The present invention discloses an array substrate manufacturing method, an array substrate and a display panel, and the method comprises: forming a gate electrode and a first electrode which is transparent on the substrate; forming an isolated layer on the substrate, and covering the isolated layer on the gate electrode and the first electrode; forming a semiconductor layer on the isolated layer; forming a medium layer on the semiconductor layer, and providing a first via hole, a second via hole and a third via hole; forming a source electrode, a drain electrode, and a second electrode on the medium layer, the source electrode and the drain electrode are connected to the semiconductor layer respectively through the first via hole and the second via hole, and the second electrode is connected to the first electrode through the third via hole to form a storage capacitance; forming a third electrode which is transparent on the medium layer, and the third electrode is connected to the drain electrode to form a pixel electrode. An utilized amount of photomasks can be decreased, technical processes can be reduced and cost can be saved during the manufacturing procedures of the array substrate in the present invention by applying the aforemention method.

主权项

1. An array substrate manufacturing method, wherein, the method comprises:
forming a gate electrode and a first electrode which is transparent on the substrate; forming an isolated layer on the substrate, and covering the isolated layer on the gate electrode and the first electrode; forming a semiconductor layer on the isolated layer; forming a medium layer on the semiconductor layer, and providing a first via hole and a second via hole in a region of the semiconductor layer correspondingly; revealing the semiconductor layer on both positions of the first via hole and the second via hole; providing a third via hole in a region of the first electrode correspondingly, and revealing the first electrode on a position of the third via hole; forming a source electrode, a drain electrode, and a second electrode on the medium layer, the source electrode and the drain electrode are connected to the semiconductor layer respectively through the first via hole and the second via hole, and the second electrode is connected to the first electrode through the third via hole to form a storage capacitance; forming a third electrode which is transparent on the medium layer, and the third electrode is connected to the drain electrode to form a pixel electrode; wherein, the gate electrode, the source electrode, the drain electrode and the second electrode are metal electrodes; the first electrode and third electrode are Indium-Tin Oxide (ITO).