发明名称 TECHNIQUES TO AVOID OR LIMIT IMPLANT PUNCH THROUGH IN SPLIT GATE FLASH MEMORY DEVICES
摘要 Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is laterally arranged between the first and second individual S/D regions, is separated from the first individual S/D region by a first channel region, and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D region. A floating gate is disposed over the first channel region, and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A word line is disposed over the first channel region, and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the word line is a concave surface.
申请公布号 KR20160087733(A) 申请公布日期 2016.07.22
申请号 KR20150071891 申请日期 2015.05.22
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 WU CHANG MING;LIU SHIH CHANG;CHEN SHENG CHIEH;CHANG YUNG CHANG
分类号 H01L27/115 主分类号 H01L27/115
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