发明名称 SELF EXAMINABLE LOGIC CIRUCIT AND INSPECTION THEREOF
摘要 PURPOSE: To enable the self-inspection of an IC by simple constitution without generating circuit delay by using a three-state pass gate and a three-state receiver in combination with a linear feedback shift register(LFSR) and a memory register. CONSTITUTION: An LFSR 30 shifts the seed pattern of data successively to form a usual scanning data inspection pattern. When a self-inspection signal is set to a second state showing the inspection mode of an IC 10, the inspection pattern is scanned within a memory register 120 to be successively used in combination logic 125 and the inspection result thereof is stored in a fourth memory register 145. Next, when the signal 110 is reset to a second state, the operation of a three-state receiver 70 is stopped and, therefore, input boundary logic 20 inputs the inspection pattern scanned by a memory register 50 through a three-state pass gate 60 started in operation and an inspection result is stored in the register 120. Therefore, the logic 20 is inspected at the same time by the same technique as internal logic 128 without generating delay. In the same way, output boundary logic 40 is inspected on the basis of the inspection pattern scanned by the register 145.
申请公布号 JPH03148079(A) 申请公布日期 1991.06.24
申请号 JP19900248975 申请日期 1990.09.20
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 ANSONII KORIIRU JIYUNIA;RICHIYAADO MAIKERU DANII;KIMU EDOWAADO ODONERU;ANDORIYUU KEEGURU;AAUIN AASAA TEITO;DEBUITSUDO EMU UU
分类号 G01R31/28;G01R31/3185;G06F11/22 主分类号 G01R31/28
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