| 摘要 |
1,091,730. Input/output control. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 1, 1966 [June 29, 1965], No. 24416/66. Heading G4A. In data communication apparatus, data sampled from cyclically scanned input lines is stored, and in response to a control signal, stored samples from only predetermined priority ones of said lines are transferred to an output during at least one scan cycle. A number of input lines are scanned sequentially, a sample from each being stored in a control word respective to the line in a recirculating delay-line store which recirculates say eleven times while a given line is being sampled once. Each control word comprises a buffer field from which a complete data character can be gated in parallel to a data processing system, an adjacent field receiving the samples and feeding the buffer field, a bit indicating if the buffer field is ready for gating out, a " priority service " bit indicating if an unsuccessful attempt was made to gate the buffer field out, a count field incremented by one each cycle of the store and indicating the point in time when the input line should be sampled, and error, status and command (transmit or receive &c.) fields. An oscillator-driven ring provides timing pulses and drives a binary counter the count of which specifies the identity of the input line currently being scanned. This count is gated to the data processing system with the control word buffer field, and is also decoded to feed an OR gate via a plugboard. The plugboard enables any input lines to be specified as priority lines. The OR gate output partially controls the setting and resetting of " priority service " bits as appropriate. A cyclic pulse generator produces pulses with a separation equal to the repetition interval of the fastest input line minus the time required to service all priority lines, and each of these pulses causes a priority cycle during which only stored characters relating to priority lines can be gated to the data processing system, and these only if said system permits. When such a character is gated, the " priority service " bit corresponding to it is reset. If any " priority service " bit remains set at the end of the cycle, further priority cycles are taken until none remains set. Successive such cycles are delineated by successive appearances of a reference control word at the read/write position of the delay-line store. A core store may replace the delay-line store. The cyclic pulse generator may be a (single-shot) multivibrator, or a field in the delay-line store stepped by one each cycle of the delay-line, or a separate binary counter. Modifications appropriate if a priority cycle is to be initiated merely following failure to service a priority line, and if two or more consecutive priority cycles are never required, are described. |
