| 摘要 |
PURPOSE:To make plural output delay variables identical and to increase the processing speed of an encoder by forming a double selective signal with an OR circuit and a NAND circuit, forming an mono-selective signal by an OR circuit and a NAND circuit and passing both the signals only with two steps of gates. CONSTITUTION:The double selective signal 2X and the mono-selective signal 1X are formed by two-stage logic circuits consisting of inverters 61, 63, 64 or inverters 63, 64 and a 6-input composite gate circuit 70 or a 4-input compositive gate circuit 80. Thereby, the output delay variable of the signal 2X coincides with that of the signal 1X and both signals 2X, 1X are obtained at the same timing. The number of stages of logic circuits for passing the signals 2X, 1X is reduced to two, the selective signal forming time can be shortened. Consequently, the processing speed of the encoder can be increased. |
