Datenverarbeitendes System aus mehreren miteinander verbundenen Datenverarbeitungsanlagen

摘要

1,195,396. Multi arocessor systems. GENERAL ELECTRIC CO. 11 July, 1967 [27 July, 1966], No. 31959/67. Heading G4A. An inter-connected computer system comprising a plurality of computer sub-systems each with a plurality of data processors, a plurality of data storage members and a central controller also includes an inter-system transfer circuits and temporary storage means for providing intercommunication between the subs-systems. As shown (Fig. 1) a first sub-system which may be as described in Specification 1,170,586 comprises processors 301, 101 and 111 memories 201-251, a central controller 321 and a central interrupt scheduler 341. A second sub-system similar elements 1111-3411. The inter-system coupling coupling apparatus or exchange box 700, which is provided in two parts 701 and 702 for communications originating from opposite directions, is connected to the respective central controllers by means of buses similar to those connecting the controllers 32 to the processors and memories. The exchange boxes thus convert between memory type signals and processor type signals. A processor requiring communication with a memory supplies signals representing the operation involved (e.g. single/double word read/write) and also the address in symbolic form (i.e. specifying programme, block and storage cell numbers). The controller linked thereto examines the symbolic address to check if it relates to data stored in an associated memory. If not, the signals are transmitted unchanged through an exchange box 701 or 702 to the other controller 32 which examines the symbolic address and establishes a communication link with the relevant memory associated therewith. Data is transmitted between the original processor and the memory by way of the temporary (two word) storage in the box 701 or 702, the two stages of transmission being effected asynchronously with respect to each other and the box 701 or 702 issuing notification signals as words are received for temporary storage. The words comprise 24 bits each and the buses connected to controllers 32 comprise from 77 to 84 leads.