发明名称 ERROR CORRECTING AND DETECTING DEVICE
摘要 PURPOSE:To correct a bit error in a single 4-bit block and to detect the error of a 8-bit burst in two optional blocks by providing a syndrome decoding means, a means to correct the error in a code word and a means to detect the error in the code word. CONSTITUTION:By the dividing circuit obtained from a formation polynomical G(X)=X<11>+X<8>+X<7>+X<4>+X+1, the generator matrix of 11 rows and 105 columns is prepared, the column vector of the matrix is an odd number weight, all are different and concerning the block divided four by four from the beginning, S4EC and A8BED functions are held. Since the word length is 64 bits, when it is compressed to the matrix of 11 rows and 75 columns, 19 blocks are selected so as to satisfy the function of a D4BED. Thus, while the number of the memory chips is suppressed to the minimum, an 8-bit burst error in two optional blocks and an adjoining 4-8-bit burst error can be detected and the error detecting capacity can be increased.
申请公布号 JPS6279530(A) 申请公布日期 1987.04.11
申请号 JP19850220664 申请日期 1985.10.03
申请人 FUJITSU LTD 发明人 ICHIKAWA HIROKO;TAKAMURA MORIYUKI;MUKOGASA SHIGERU;IHI TAKASHI
分类号 G06F11/10;G06F12/14;G06F12/16;G06F21/24 主分类号 G06F11/10
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