发明名称 SHIFTING CIRCUIT
摘要 PURPOSE:To reduce a space required for wiring, by constituting a shifter of first through n-th multiplexers and n+1-th through n+m-th multiplexers, and executing a prescribed left shift. CONSTITUTION:For instance,in the case of executing a left shift to '0'-7 bits, a control circuit 20 executes decoding so as to show it by the sum of shift numbers 2<0>, 2<1> and 2<2> designated by a shift number designating signal SFT 19, and controls corresponding select signals S112, S214 and S316. As a result, by multiplexers 11, 13, 15 and 17, a desired left shift is executed. Also, in the case of executing a left shift of 8 bits, the control circuit 20 sets all of the select signals S112, S214 and S316 and Se.118 to '1'. In this state, a left shift of 1, 2, 4 and 1 bits is executed by the multiplexers 11, 13, 15 and 17 and a left of total 8 bits is executed. In such a way, a physical space required for wiring can be reduced.
申请公布号 JPS63211430(A) 申请公布日期 1988.09.02
申请号 JP19870045557 申请日期 1987.02.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UEDA KATSUHIKO
分类号 G06F7/00;G06F7/76 主分类号 G06F7/00
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