发明名称 VECTOR COMPUTING SYSTEM
摘要 PURPOSE:To immediately execute an arithmetic instruction, by instructing the start of the execution of an arithmetic operation for the next vector element replying to the completion of the execution of the arithmetic operation while a start instruction holding flag is set, and resetting the start instruction holding flag. CONSTITUTION:A microinstruction is read out from a control storage circuit 1, and is stored in a microinstruction register 3, and an arithmetic operation start bit S in the register 3 is supplied to an arithmetic control circuit 15. And while the arithmetic operation is executed, the signal S is set at a start instruction holding flag FF205 via a line 101 and an AND gate 212. The FF205, when the start instruction of the next arithmetic operation being issued by the microinstruction during the execution of the arithmetic operation, holds the instruction until the arithmetic operation under execution is completed. And the FF205 is reset corresponding to the completion of the execution of the arithmetic operation, and is set when the completion of the execution of the arithmetic operation and the start of the next execution are performed simultaneously.
申请公布号 JPS641059(A) 申请公布日期 1989.01.05
申请号 JP19870165686 申请日期 1987.07.01
申请人 NEC CORP 发明人 ISHII HIDESHI
分类号 G06F9/305;G06F9/22;G06F15/78;G06F17/10;G06F17/16 主分类号 G06F9/305
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