| 摘要 |
PURPOSE:To efficiently use a data memory by providing the data memory where data is held, a FIFO memory where a writable idle address is preserved, and a scheduling memory where addresses are preserved in order. CONSTITUTION:All addresses on a cell preservation RAM (data memory) 1 are stored in a FIFO memory 2. Each time a cell arrives, the write address from the memory 2 is taken out and a data block is written in this address through a write control circuit 3. At this time, the written address is written in a schedule RAM (scheduling memory) 4 also. At the time of reading out data from the RAM 4, the address on the RAN 1 is received from the RAM 4 corresponding to a time pointer 5 for read and data in this address is sent to an exchange switch part of the next stage. Simultaneously, the address read out from the RAM 4 is deleted, and this address is written in the memory 2. That is, the address is returned to the memory 2. Thus, the write address is quickly determined.
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