| 摘要 |
PURPOSE:To attain circuit integration by providing an exclusive OR element receiving a couple of data outputs of a data flip-flop, and a final stage exclusive OR element integrating outputs of the exclusive OR elements and sending a signal to a loop filter. CONSTITUTION:The circuit is provided with plural parallel data flip-flops 11-14 receiving a polyphase PSK modulated wave signal and a clock signal, and phase shifters 21-23 whose phase is deviated by pi/n each with respect to a clock signal input line. Then a signal is sent to a loop filter from a final stage exclusive OR element 40 through exclusive OR elements 31, 32 receiving outputs of the flip-flops 11-14 in pairs. Thus, the phase shifters act like shift registers without use of a filter element comprising of capacitors and resistors, adder/ subtractor circuits and a multiplier element/and the circuit is integrated entirely. |
