| 摘要 |
<p>PURPOSE: To perform a high-speed operation with a relatively less gate amount by allowing an adder to have the serial connection constitution of cells for generating intermediate carry signals. CONSTITUTION: Respective blocks are provided with the 2-4 pieces of 1-bit cells. In such blocks (for instance (j)=0-2), two ripple carry outputs Cout 0(i) and Cout 1 (i) are generated. In the start cells of the respective blocks, carry inputs Cin0 and Cin1 are respectively defined as '0' and '1'. The two carry outputs Cout generate the carry output Cout block (j) of the block at present by being combined with a carry input Cin block (j) inputted to the block at present. The chaining of the two carries (Cout0-Cin0 and Cout1-Cin1) are simultaneously and successively propagated in all the blocks of (j)=0-2. Thus, the delay time of a full adder is reduced and the complication of a circuit is suppressed to be relatively low.</p> |
