| 摘要 |
<p>PURPOSE:To make the transfer processing high in efficiency by allowing a control unit to manage number of transmission and incoming buffers for a packet data and publicating an outgoing incoming unit address with priority for packet transfer based on the information. CONSTITUTION:A unit address generating circuit 102 publicates an address to collect the buffer state of an interface unit under the control of a control discrimination circuit 101 in a control unit 1. A unit 2 having the address stores a packet inputted from an external device 3 via an input/output interface circuit 204 for the communication with the device 3 to a transmission buffer 205 and stores a packet for the device 3 to a reception buffer 206. The number of packets addressed to other interface unit stored in the buffer 205 and the number of packets stored in the buffer 206 are stored in a unit state management table 203 via the control circuit 201 and the information is returned to the unit 1. A matrix status management table 103 of the unit 1 stored the collected information.</p> |
