| 摘要 |
PURPOSE: To provide a clock de-skew circuit from which the cause of the generation of skew based on various kinds of factors is removed. CONSTITUTION: A clock de-skew circuit is provided with a variable delay module 10 and a control module 11. This veriable delay module 10 has an input terminal 20 which receives a digital input clock signal, control terminals 22a and 22b which receive an analog control signal and delay circuits 23-1 to 23-N which propagate the input clock signal from the input terminal 20 to buffers 29a, 29b and 29c. Thus, a certain type of signal edge is delayed only by the size of a control signal for a certain time interval changing in a continuous mode. The control module 11 generates control signals RCV and FCV so that an exact one cycle delay time is generated between an input signal and a feedback signal. |
