| 摘要 |
PURPOSE:To attain the normal interruption processing by providing an invalid flag flip-flop which is reset by an NMI input signal showing the invalidity of the contents of an operand register when a cache error occurs. CONSTITUTION:A main storage 3 is provided together with a microprocessor part 1 and a cache part 2 set between both parts 1 and 3. If a cache error is detected at the part 2 while the microprocessor 1 is reading the part 3, a cache error signal 201 is inputted to a non-mask interruption NMI signal of the microprocessor 1 via a means provided newly. Furthermore a flip-flop of an invalid flag 13 is set to show the validity of the contents of an operand register 12 fetched by the signal 201. Then a means is added to turn on an execution instruction at occurrence of an error after the flip-flop is set. Thus the normal interruption processing is attained. |
