DELAY ANALYSIS SYSTEM FOR LOGIC CIRCUIT,申请号JP19920128416-传众专利搜索

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发明名称	DELAY ANALYSIS SYSTEM FOR LOGIC CIRCUIT
摘要
申请公布号	JPH0660143(A)	申请公布日期	1994.03.04
申请号	JP19920128416	申请日期	1992.05.21
申请人	NEC CORP	发明人	BITO TATSUSHIGE
分类号	G06F17/50;(IPC1-7):G06F15/60	主分类号	G06F17/50
代理机构		代理人
主权项
地址

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