发明名称 FORMATION OF MULTILAYER INTERCONNECTION
摘要 PURPOSE:To accurately form a resist pattern for forming a connecting hole in a layer insulating film in a multilayer interconnection forming method. CONSTITUTION:After forming a wiring layer 18 made of aluminum or an aluminum alloy on an insulating film 16 covering the upper surface of a semiconductor substrate 10, the wiring layer 18 is covered and a layer insulating film 20 such as silicon oxide is formed, and then a reflection preventive film of TiN, etc., is formed on the surface of the insulating film 20. After forming a resist layer on the reflection prevented film, an opening corresponding to a desired connection hole is formed by applying an exposure and developing treatment to this resist layer. And a connecting hole 28 is formed by selectively the insulating film 20 with the resist layer having the opening as mask. After removing the resist layer, a wiring layer 30 is formed on the upper surface of the substrate, but a remaining portion 22A of the reflection preventive film may be used as part of the wiring layer 30.
申请公布号 JPH0685075(A) 申请公布日期 1994.03.25
申请号 JP19930198889 申请日期 1993.07.16
申请人 YAMAHA CORP 发明人 MATSUMOTO YASUHIKO;HATTORI ATSUO
分类号 H01L21/3205;H01L21/027;H01L21/768;H01L23/52;(IPC1-7):H01L21/90;H01L21/320 主分类号 H01L21/3205
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