Signal shaper for input signal wave form reshaping

摘要

The input clock pulse signal (IN) is delayed by a delay circuit (11), with a delay value which is changed monotonously by a control signal. The circuit transmits a first delayed clock pulse signal (OUT-A), with a specified top limit of the delay value. A second variable delay circuit (12) transmits a second delayed clock pulse signal (OUT-B) from a specified processing of either the input clock pulse signal, or the first delayed signal. A control section (13) compares the phases of the input clock pulse and the first delayed clock pulse signals, and generates a control signal accordingly. An SR flip-flop completes the assembly.