发明名称 ELECTRONIC CIRCUIT, IN PARTICULAR CAPABLE OF IMPLEMENTING A NEURAL NETWORK, AND NEURAL SYSTEM
摘要 An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.
申请公布号 US2016203401(A1) 申请公布日期 2016.07.14
申请号 US201414910984 申请日期 2014.09.29
申请人 COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES 发明人 DURANTON Marc;PHILIPPE Jean-Marc;PAINDAVOINE Michel
分类号 G06N3/063 主分类号 G06N3/063
代理机构 代理人
主权项 1. A circuit designed to implement a neural network, comprising at least: a series of elementary modules, called neuro-blocks, designed to implement an assembly of neurons, said neuro-blocks being grouped together in branches, a branch being composed of a group of neuro-blocks and of a broadcasting bus, the neuro-blocks being connected to said broadcasting bus; a routing unit connected to the broadcasting bus of said branches, carrying out at least the routing and the broadcasting of data to and from said branches; a transformation module connected to the routing unit via an internal bus and designed to be connected, at the input of said circuit, to an external databus, said module carrying out the transformation of the format of the input data carried by said external bus, a message of N input words with x bits coded in parallel being transformed into a message of N words with x bits coded in series, the N words being parallelized over the internal bus at the output of said module, one wire of the bus being dedicated to one word, the words being broadcast over the broadcasting buses of the branches and the other internal components of said circuit via the routing unit with the same serial coding, in such a manner that all the processing operations internal to said circuit are carried out according to a serial communications protocol.
地址 Paris FR