发明名称 |
III-V CMOS integration on silicon substrate via embedded germanium-containing layer |
摘要 |
After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor. |
申请公布号 |
US9412744(B1) |
申请公布日期 |
2016.08.09 |
申请号 |
US201514609507 |
申请日期 |
2015.01.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Cheng Cheng-Wei;Sadana Devendra K.;Shiu Kuen-Ting |
分类号 |
H01L29/66;H01L27/092;H01L27/12;H01L29/205;H01L29/32;H01L21/02;H01L21/8252 |
主分类号 |
H01L29/66 |
代理机构 |
Scully, Scott, Murphy & Presser, P.C. |
代理人 |
Scully, Scott, Murphy & Presser, P.C. ;Percello, Esq. Louis J. |
主权项 |
1. A semiconductor structure comprising
a substrate comprising a handle substrate, a compound semiconductor template layer present on the handle substrate, and a buried insulator layer present on the compound semiconductor template layer; a top elemental semiconductor layer portion present on a first portion of the substrate and in contact with a top surface of the buried insulator layer; and a stack of compound semiconductor layers present on a second portion of the substrate and comprising a compound semiconductor buffer layer in contact with a top surface of the compound semiconductor template layer and a top compound semiconductor layer present on the compound semiconductor buffer layer, wherein a lower portion of the stack is laterally surrounded by the buried insulator layer, and wherein an upper portion of the top compound semiconductor layer protrudes above a horizontal plane including a top surface of the top elemental semiconductor layer portion. |
地址 |
Armonk NY US |