Lithography process monitoring of local interconnect continuity

摘要

Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate lines are formed. Next, a first group of two or more local interconnect lines landing on transistor gates and formed substantially perpendicular to the first set of transistor gate lines and electrically coupled therewith is formed using a first lithography pass. A second group of two or more local interconnect lines landing and formed substantially perpendicular to the second set of transistor gate lines and electrically coupled therewith is formed during second lithography pass. For some technologies, a third set of transistor gate lines is formed along with a third group using a third lithography pass.

主权项

1. A method to form local interconnects in a continuity test structure, the method comprising:
forming a set of first transistor gate lines comprising multiple subsets of first transistor gate lines, each subset of first transistor gate lines comprising multiple parallel first transistor gate lines; forming a set of second transistor gate lines comprising multiple subsets of second transistor gate lines, each subset of second transistor gate lines comprising multiple parallel second transistor gate lines; forming, using a first lithography pass, a group of first local interconnect lines formed substantially perpendicular to the set of first transistor gate lines and electrically coupled therewith, the group of first local interconnect lines being formed such that each subset of first transistor gate lines is only contacted by a pair of adjacent first local interconnect lines and such that each first local interconnect line has at least one end that contacts one of the multiple subsets of first transistor gate lines; and forming, using a second lithography pass, a group of second local interconnect lines formed substantially perpendicular to the set of second transistor gate lines and electrically coupled therewith, the group of second local interconnect lines being formed such that each subset of second transistor gate lines is contacted by a pair of adjacent second local interconnect lines and such that each second local interconnect line has at least one end that contacts one of the multiple subsets of second transistor gate lines.