Method of eliminating poor reveal of through silicon vias

摘要

A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front side, a back side and partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side. A region of the back side of the wafer is patterned and etched to expose and reveal a portion of each of the plurality of through silicon vias. A metal layer is deposited on the back side of the wafer to form a back side metallization. The metal layer covers all of the back side including the etched region of the back side and the exposed portions of each of the through silicon vias.

主权项

1. A method, comprising:
obtaining a wafer having a front side, a back side and a plurality of partially etched and metalized through silicon vias (TSVs), wherein each partially etched and metalized TSV of the plurality of partially etched and metalized TSVs extends from a portion of the front side through a portion of the back side of the wafer and terminates before reaching an end surface of the back side of the wafer; patterning and etching a region of the back side of the wafer to expose and reveal a portion of each partially etched and metalized TSV of the plurality of partially etched and metalized TSVs,
wherein the patterning includes applying a mask on the back side of the wafer; andwherein the portion of each partially etched and metalized TSV of the plurality of partially etched and metalized TSVs includes a trench portion of each partially etched and metalized TSV of the plurality of partially etched and metalized TSVs, the trench portion being a portion of a sidewall of each partially etched and metalized TSV of the plurality of partially etched and metalized TSVs and depositing a metal layer on the back side of the wafer to form a back side metallization, the metal layer covering all of the back side of the wafer including the etched region of the back side of the wafer and the exposed portions of each partially etched and metalized TSV of the plurality of partially etched and metalized TSVs.