发明名称 PROJECTION EXPOSING MASK
摘要 PURPOSE:To shorten the time for inspecting the pattern to be formed on a resist and wafer by forming the inspecting patterns, the boundary marks and the non-boundary marks respectively in specific positions. CONSTITUTION:The inspecting patterns 2 and boundary marks 3a to 3c of this mask are formed in the regions enclosing the patterns 1a to 1f for forming the element of a semiconductor chip and the non-boundary marks 4a to 4g are formed between the patterns 1a to 1f. The searching of the patterns 2 by tracing the marks 4a to 4g, 3a to 3c is then facilitated. The indicating of the routes to exposing corner marks 5a to 5d by forming the patterns 2 in the same manner as before and by forming direction indicating marks 6a to 6m in the regions enclosing the patterns 1a to 1f and between the patterns 1a to 1f is preferable as well.
申请公布号 JPH03269433(A) 申请公布日期 1991.12.02
申请号 JP19900069113 申请日期 1990.03.19
申请人 FUJITSU LTD 发明人 MUNETA TAKAYUKI
分类号 G03F1/44;G03F1/84;H01L21/027;H01L21/66 主分类号 G03F1/44
代理机构 代理人
主权项
地址