| 摘要 |
PURPOSE:To prevent an output signal from being affected with noise superimposed on a reception data clock by providing a control signal width detection circuit inverting the frequency UP and DOWN control of an internal clock and a control signal selection circuit receiving an output of a phase difference detection circuit and an output of the control signal width detection circuit so as to increase or decrease the internal clock frequency. CONSTITUTION:A counter 12d receives a phase difference output by a phase difference detection circuit 11 and switches whether a phase difference between a clock CK1 of a received data and a clock CK2 from a VCO is led or lagged. A control signal selection circuit 13 consists of AND gates 13a, 13b and a NOT gate 13c and gives an output of control in a direction of the recognition of a control signal width detection circuit 12 (frequency UP or frequency DOWN) by a phase difference outputted form the phase difference detection circuit 11. That is, in the case of frequency UP, a signal is outputted to a frequency UP output terminal U and in the case of frequency DOWN, a signal is outputted to a frequency DOWN output terminal D. |
