| 摘要 |
PURPOSE:To execute one time of multiplication in one machine cycle by storing a signal into a coefficient memory circuit after decoding by a decoder circuit, reading out the signal from the coefficient memory circuit when executing the multiplication, and inputting it to a multiplier. CONSTITUTION:The decoder circuit 13 which decodes a multiplier or a multiplicand, and the coefficient memory circuit 17 which stores plural multipliers or multiplicands decoded by the decoder circuit 13 are provided. The multiplication of the multiplier or the multiplicand stored in the coefficient memory circuit 17 with the read out and inputted multiplicand or multiplier of an opponent is performed according to the Booth's algorithm. In such a way, either the multiplier or the multiplicand to be multiplied at the multiplier 18 is decoded by the decoder circuit 13 in advance, and is stored in the coefficient memory circuit 17. Thereby, it is possible to accelerate multiplication time by a time not requiring for decoding. |
