发明名称 ENCODER AND DECODER
摘要 <p>PURPOSE:To accelerate coding processing and decoding processing by completing readout when an address shows the one in which the last non-zero coefficient exists in a block and attaching an EOB(END OF BLOCK) code when a conversion coefficient in the block is coded. CONSTITUTION:When the conversion coefficient is written on memory 101, the coefficient in the block is written according to constant sequence, and also, it is decided whether the conversion coefficient to be written is zero or non-zero by a non-zero coefficient decision means 102, and when the conversion coefficient is the non-zero coefficient, the address is stored in a non-zero coefficient address storage means 104. When the conversion coefficient in the block is coded, the conversion coefficient in the block is read out from the memory 101 sequentially, and it is compared with the address stored in the non-zero coefficient address storage means 104 by an address comparison means 105, and the readout is completed when the address shows the one in which the last non-zero coefficient exists in the block, and the EOB(END OF BLOCK) code is added. In such a way, the coding processing and the decoding processing can be accelerated.</p>
申请公布号 JPH03289789(A) 申请公布日期 1991.12.19
申请号 JP19900090823 申请日期 1990.04.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMANE YASUHIKO;HASEBE TAKUMI
分类号 H04N19/60;H04N19/423;H04N19/91 主分类号 H04N19/60
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