| 摘要 |
PURPOSE:To simplify the constitution of a comuting element and to reduce the capaity of a ROM by specifying the address to a memory device and replacing row and column addresses while matching with the execution of operation of an one-dimensional orthogonal transformer. CONSTITUTION:At the time of writing, an address is applied so as to be advanced in a row direction and the calculated result of an one-dimensional discrete cosine transformation (DCT) computing element 4 is written in accor dance with a row direction address in a memory device 2. At the time of read ing, the switching circuit 18 in an address generator is switched to switch a row address to a column address. Thereby, address specification in the memory device 2 is changed to the order of the column direction and the data of the device 2 are read out to the computing element 6. At the end of the address reading, the reading mode is changed to the writing mode again and the circuit 18 is switched so that addresses are advanced in the row direction again. Thus, DCT operation is repeated. |
