| 摘要 |
PURPOSE:To reduce a circuit, to eliminate a memory and to speed up an operation by obtaining the sums S0 and S1 of digits corresponding to digits which come to '0' and '1' by binary decimal points in an addition circuit and setting them to be a correction item. CONSTITUTION:A coefficient 1/K (X and K are natural numbers and K=3 in this case) is rounded off to data X which is binary-expressed. The first addition circuits 10 and 11 obtain the sum S0 of the digits of data X corresponding to the digit which becomes '0' when the coefficient 1/K is expressed by the binary decimal, and the sum S1 of the digit of data X corresponding to the digit becoming '1'. Decoders 12 and 13 decode the sums S0 and S1 corresponding to the first addition circuits 10 and 11. An encoder 14 outputs the prescribed correction term from decoding results outputted from the decoders 12 and 13. A second addition circuit 15 outputs the desired coefficient result by using the correction term and said data, which the encoder 14 outputs. Thus, a circuit scale can be reduced and the memory can be eliminated, whereby operation item can be shortened. |
