| 摘要 |
1375794 Automatic timing; data transmission systems INTERNATIONAL BUSINESS MACHINES CORP 8 Feb 1972 [19 Feb 1971] 5691/72 Headings H3A and H4P In a self-clocking data transmission system strobe pulses normally at the bit frequency of the received data are generated locally by two cycling counters when their combined counts equal a predetermined value, and to maintain the strobe pulses at the centre of each bit counters are advanced or retarded according to their state of count at the arrival of the leading stage of a data pulse for one counter and the trailing edge for the other counter. In Fig. 1 the leading and trailing edges of the first pulse of a stream of data at input 1 via detectors 2 and 3 set latches L1, L2, whereby cycling counters CRTA and CRTB are driven by clock 4 via AND gate 6 for CRTA and via a half-bit period delay 16 and AND gate 9 for CRT3. Both counters cycle for 0-7, CRTA having a nominal count of 0 at the leading edges of data pulses and CRTB a count of 0 at the trailing edges, whereby upon the combined count reaching 9 adder circuit 14 provides a strobe pulse to pulse detecting circuit 15 to sample the data signal and give a 0 or 1 output accordingly. Should the leading edge be early whereby counter CRTA still has a count of 7, at the next clock pulse AND gate 5 opens to step CRTA two places to a count of 1; alternatively should the leading edge be late when CRTA has a count not equal to 0 (but also not equal to 7) then AND gate 7 via inverter I inhibits AND gate 6 for one clock period thereby inhibiting the stepping of CRTA. Counter CRTB and AND gates 10, 9 and 8 operate in a similar fashion on the trailing edges of data pulses. The arrangement can correct any distortion with a predetermined limit, extra pulses to be added or inhibited can be produced for different levels of distortion. |
