| 摘要 |
PURPOSE:To secure the synchronization among plural demodulation data for each sample or block by reading the NRZ data out of a memory with a master bit clock and a master LRCK pulse received from a master PLL modulation block. CONSTITUTION:The write address pointer of a memory 3 is initialized with an LRCK pulse generated from a demodulation block 1. Then the address pointers are increased one by one by a bit clock and at the same time the demodulated NRZ data are written into the memory by an amount equal to one sample. Meanwhile the read address pointer of the memory 3 is initialized with a master LRCK pulse generated from a master PLL modulation block 4. Then the address pointers are increased one by one by a master bit clock and at the same time the data are read out of the memory 3 by an amount equal to one sample. In the same way, the data are read out of a memory 3' by an amount equal to one sample. Thus it is possible to secure the synchronization between the demodulated data a2 and c2 for each sample. |
