| 摘要 |
<p>PURPOSE:To realize high access time by providing a means changing the logic level of a detection means composed of inverter construction according to the state of bit line electric potential. CONSTITUTION:A circuit composed of transistors P54, P55, N55, and N54 detects charge to bit lines 57/58 and continues generating pulses from a nordal point 55 during the charge. Inverter circuits (INV) 3/2 waveformingly form the generated pulses to be delayed, and the translator P53 changes the logic level of the precharge circuit composed of the logic level N53, P52, and N52 of the inverter circuit composed of the transistors N52 and P52 to the logic level of a sense circuit. Thus, the access time of a memory cell reading related to the charge of the bit line can be speeded up.</p> |
