| 摘要 |
PURPOSE:To perform efficiently refresh of a DRAM and the DRAM access of a CPU by dividing memory areas to even areas and odd areas to avoid the competition on the memory between the access cycle of the CPU and the refresh cycle. CONSTITUTION:When a CPU 7 accesses an even address, the address from the CPU 7 is given to a DRAM 4 for even address, and the normal memory R/W cycle is executed. At this time, the signal on a line 1 becomes ''1'' to make refresh of a DRAM 1 possible, and an address where contents should be refreshed is given to the DRAM 1 from a counter circuit 6 by a 2-1 selector circuit 5. The counter circuit 6 is counted up simultaneously with the end of refresh to generate an address for the next refresh cycle. Though the CPU 7 accesses the even address, a memory request control signal is sent to the DRAM 1 for odd address also for the purpose of performing refresh. |
