| 摘要 |
PURPOSE:To speed up area detection processing by constituting the titled circuit of hardware, and executing the processing in parallel. CONSTITUTION:An area boundary value array data is sent out to a data bus 1 of a data processor, decoded by a demultiplexer, and boundary values Xi (i=0-N-1) are stored in N pieces of registers Ri (i=0-N-1). The boundary values Xi are placed in a descending order, and set to X0>X1>X2>...XN-1. At the time of C<Xi-1, Xi, a logical condition of an AND circuit ANDi is not formed, and at the time of C>Xi-1, Xi, as well, said condition is not formed. AT the time of Xi<C<Xi-L, the logical condition of ANDi is formed, and '1' is outputted. When the AND condition is formed, when i=k is set, an area number corresponding to this 'k', for instance, 'k' is detected, encoded by an encoder 3, and sent out to a data bus.
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