发明名称 MEMORY AMPLIFYING CIRCUIT
摘要 PURPOSE:To reduce the scale of a sense amplifier and reduce power consumption by allowing the sense amplifier to perform only one of amplifications for transfer of information, which is obtained by differential amplification of the information difference between a memory cell and a dummy cell, to input/ output paths to prevent the sense amplifier from simultaneously taking charge of two operations. CONSTITUTION:When a word line W is selected by a row decoder circuit 1, a bit line selecting signal A1 goes to the high level, and all selecting transistors TRs and sense amplifiers connected to this signal A1 are turned on and are made operatable. At this time, a bit line selecting signal A2 goes to the low level, and selecting TRs and sense amplifiers connected to this signal are turned off and are made unoperatable. Information of a memory cell M is outputted to a bit line D1, and simultaneously, a dummy word line DW is selected by a dummy word circuit B1, and information of a dummy cells DM is outputted to a bit line D'1, and the information difference between bit lines D1 and D'1 is amplified by a sense amplifier S2.
申请公布号 JPS63179497(A) 申请公布日期 1988.07.23
申请号 JP19870011619 申请日期 1987.01.20
申请人 NEC CORP 发明人 SEGAWA MACHIO
分类号 G11C11/401;G11C11/34;G11C11/409 主分类号 G11C11/401
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