发明名称 CLOCK SYNCHRONIZING SYSTEM AT LOOPBACK
摘要 PURPOSE:To prevent a phase locked oscillator from being oscillated by allowing a switching circuit to switch a clock from an N system into an E system with a loopback control signal at the loopback control. CONSTITUTION:A switching circuit 32 usually selects the clock of the N system and gives it to a phase locked oscillator 33. In this case, loopback is formed at the input section of a multiplex/demultiplex circuit 30 at loopback control because of the connection of input and output lines. On the other hand, the switching circuit 32 selects the E system clock from the N system with a loopback(LB) control signal. Since no clock loop through a clock path is formed at loopback, the oscillation of the phase locked oscillator 33 is prevented.
申请公布号 JPH0358534(A) 申请公布日期 1991.03.13
申请号 JP19890195289 申请日期 1989.07.26
申请人 FUJITSU LTD 发明人 TANIGUCHI TAKAYUKI;FUKUDA NOBUO
分类号 H04J3/06;H04L7/00 主分类号 H04J3/06
代理机构 代理人
主权项
地址