| 摘要 |
PURPOSE:To perform current limit operation stably with substantially no response lag even upon abrupt increase of load current by constituting a current limit circuit of a combination of a comparator, a flip-flop operable with the output of comparator and a synchronizing pulse, and an AND gate for turning a PWM pulse ON/OFF based on the output of the flip-flop. CONSTITUTION:When the load current is lower than a preset limit current level, a comparator 7 does not function and has L output level and thereby a flip-flop 10 is reset by a synchronizing pulse and has H output level. Consequently, a PWM pulse is applied, as it is, on the gate of a FET 2 through an AND gate 8 thus subjecting a motor 1 to chopper control according to a PWM pulse train. When the current value detected through a shunt 3 exceeds the current limit level due to abrupt increase of load torque of the motor 1, output of the comparator makes a transition from L to H to cause transition of the output of the flip-flop from H to L thus pulling the output of the AND gate 8 down to L level. |
