Prüfbare RAM-Architektur in einem Mikroprozessor mit eingebettetem Cache-Speicher
摘要
A microprocessor (100) with embedded cache memory (204) is disclosed. In a "test mode" of operation, caches (204) are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches (204) allows the testing of the functionality of the cache memory arrays (204). External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized. <IMAGE>
申请公布号
DE69126756(T2)
申请公布日期
1998.01.29
申请号
DE1991626756T
申请日期
1991.10.10
申请人
LSI LOGIC CORP., MILPITAS, CALIF., US
发明人
FUCCIO, MICHAEL, SANTA CLARA, CALIFORNIA 95051, US;DESAI, SANJAY, SUNNYVALE, CALIFORNIA 94086, US