| 摘要 |
<p>A clock signal supplying integrated circuit includes a clock tree constituted of only 3.3V-operating buffers connected in the form of a tree having three cascaded stages. A first stage buffer of the clock tree is connected to a clock input terminal, and a plurality of third stage buffers are connected to a clock input of 3.3V-operating flipflops and a clock input of 2.5V-operating flipflops. Thus, the clock propagation time from the clock input terminal to the clock input of 2.5V-operating flipflops is made equal to the clock propagation time from the clock input terminal to the clock input of 3.3V-operating flipflops, so that the in-phase clocks signals are distributed to the 3.3V-operating flipflops and the 2.5V-operating flipflops, regardless of variation of the diffusion condition of the LSI manufacturing process and/or the operating temperature of the LSI, and with using no delay circuit which was required in the prior art for compensating for the difference in the propagation time between the clock signal applied to 2.5V-operating flipflops and the clock signal applied to 3.3V-operating flipflops. <IMAGE></p> |
