发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To fine a metal dot pattern, and at the same time to inhibit increase in via resistance in a semiconductor device having multilayer interconnection with stacked via structure. SOLUTION: A first conductive film for wiring on a semiconductor substrate 101 is etched with a first via contact 106 as a mask to form a first layer wiring 1 03A, and a second interlayer insulation film 108 is deposited. Then the upper end part of the first via contact 106 is made to project from the upper surface of the second interlayer insulation film 108, a second conductive film 109 for wiring and a third interlayer insulation film 110 are deposited, and a second via contact 111 is formed at the upper side of the first via contact 106 in the third interlayer insulation film 110. The second conductive film 109 for wiring is etched with the second via contact 111 as the mask, to form a metal dot pattern 109B.
申请公布号 JP2001313334(A) 申请公布日期 2001.11.09
申请号 JP20000128874 申请日期 2000.04.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAMAOKA EIJI;NAKAGAWA HIDEO;UEDA TETSUYA
分类号 H01L23/522;H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L23/522
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