| 摘要 |
PURPOSE: An input signal generation circuit of a command decoding circuit improving a setup/hold margin is provided, which prevents the decrease of an operation speed of a Rambus DRAM and thus prevents a misoperation. CONSTITUTION: The circuit generating an input signal of a command decoding circuit in a Rambus DRAM comprises the first signal transfer path(10) delaying an input signal and the second signal transfer path(12) delaying the input signal by the second delay time longer than the first delay time. A number of latches(14a,14b,14c) latch an output signal of the first and the second signal transfer path respectively by being synchronized to a reference signal. And a delay resistor(RD) is inserted into the first signal transfer path and delays the input signal additionally. The delay resistor is formed with a silicon material. The reference signal includes a clock signal and a complementary clock signal, and the latch devices are D flip flops.
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