发明名称 |
Interlocked synchronous pipeline clock gating |
摘要 |
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
|
申请公布号 |
US7308593(B2) |
申请公布日期 |
2007.12.11 |
申请号 |
US20060376544 |
申请日期 |
2006.03.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
JACOBSON HANS M.;KUDVA PRABHAKAR N.;BOSE PRADIP;COOK PETER W.;SCHUSTER STANLEY E. |
分类号 |
H04L5/00;G06F1/32;G06F9/30;G06F9/38;G06F9/44 |
主分类号 |
H04L5/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|