HIGH VOLTAGE DEPLETION FET EMPLOYING A CHANNEL STOPPING IMPLANT

摘要

A high voltage field effect transistor device is fabricated (200). A substrate is provided (202). Isolation structures and well regions are formed therein (204). Drain well regions are formed within the well regions (206). An n-type channel stop resist mask is formed (208). N-type channel stop regions and n-type surface channel regions are formed (210). A p-type channel stop resist mask is formed (212). P-type channel stop regions and p-type surface channel regions are then formed (214). A dielectric layer is formed over the surface channel regions (216). Source regions are formed within the well regions (218). Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions (220). Top gates are formed on the dielectric layer overlying the surface channel regions (222).