| 摘要 |
PROBLEM TO BE SOLVED: To provide a scan flip-flop circuit, a scan test circuit, a semiconductor integrated circuit, and a scan test method in which a reduction in operating speed or an increase in operating current during normal operation are suppressed.SOLUTION: A selection circuit SEL1 of a scan flip-flop circuit includes a circuit in which a series circuit in which an MP1 connected to a scan data input terminal si, an MP2 connected to the inverted terminal of a scan enable input terminal se, and an MP3 connected to a data input terminal d are connected in series and a series circuit in which an MP4 connected to the scan enable input terminal se and an MP5 connected to the inverted terminal of the scan enable input terminal se are connected in series are connected in parallel, the selection circuit SEL1 selecting and outputting either ordinary data or test data in accordance with the logic value of the scan enable input terminal se, the size of the MP2 being smaller than the sizes of other MOSFETs.SELECTED DRAWING: Figure 1 |
