发明名称 Modification of prefetch depth based on high latency event
摘要 A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data processing system based on a memory access request received from a processor core. The memory controller receives an indication of an upcoming high latency event affecting access to the system memory. In response to the indication, the memory controller temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming high latency event.
申请公布号 US9378144(B2) 申请公布日期 2016.06.28
申请号 US201314036284 申请日期 2013.09.25
申请人 International Business Machines Corporation 发明人 Dodson John S;Dooley Miles R.;Goodman Benjiman L.;Joyner Jody B.;Powell Stephen J.;Retter Eric E.;Stuecheli Jeffrey A.
分类号 G06F12/08;G06F9/30;G06F9/38 主分类号 G06F12/08
代理机构 代理人 Russell Brian F.;Bennett Steven L.
主权项 1. A method of prefetching in a data processing system, the method comprising: in a prefetch unit in a memory controller for a system memory at a lowest level of a memory hierarchy of the data processing system, establishing a prefetch stream based on a memory access request received by the memory controller from a processor core; during operation of the memory controller, the memory controller receiving an indication of an upcoming memory refresh cycle of the system memory that will temporarily increase access latency to the system memory; and in response to the indication of the upcoming memory refresh cycle, the memory controller temporarily increasing a prefetch depth of the prefetch stream with respect to the system memory and issuing, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming memory refresh cycle.
地址 Armonk NY US