METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH N-TYPE AND P-TYPE FIELD EFFECT TRANSISTORS HAVING SYMMETRIC SOURCE/DRAIN JUNCTIONS AND OPTIONAL DUAL SILICIDES

摘要

In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

主权项

1. A semiconductor structure comprising:
a substrate; a first transistor above said substrate and comprising:
a first semiconductor body comprising first source/drain regions and a first channel region between said first source/drain regions;a first gate structure adjacent to said first channel region;first raised source/drain regions on said first source/drain regions; and,a first gate sidewall spacer between said first raised source/drain regions and said first gate structure; a second transistor above said substrate and comprising:
a second semiconductor body comprising second source/drain regions and a second channel region between said first source/drain regions;a second gate structure adjacent to said second channel region;second raised source/drain regions on said second source/drain regions; and,a second gate sidewall spacer between said second raised source/drain regions and said second gate structure, said first gate sidewall spacer and said second gate sidewall spacer being discrete portions of a first dielectric layer; a second dielectric layer above said first transistor immediately adjacent to said first raised source/drain regions; a third dielectric layer on said second dielectric layer; and, a fourth dielectric layer on said third dielectric layer and further extending laterally over said second transistor so as to be immediately adjacent to said second raised source/drain regions.