发明名称 FINE PATTERNING METHODS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME
摘要 A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the mask layer, forming a connection spacer between the sacrificial patterns and first spacers that are spaced apart from each other with the pair of sacrificial patterns interposed therebetween and covering side surfaces of the sacrificial patterns, etching the upper mask layer using the first spacers and the connection spacer as an etch mask to form upper mask patterns, forming second spacers to cover side surfaces of the upper mask patterns, etching the lower mask layer using the second spacers as an etch mask to form lower mask patterns, and etching the underlying layer using the lower mask patterns as an etch mask.
申请公布号 US2016247725(A1) 申请公布日期 2016.08.25
申请号 US201615141860 申请日期 2016.04.29
申请人 Samsung Electronics Co., Ltd. 发明人 Kim Gyeong-seop;Kim Sungbong;Kim Myeongcheol
分类号 H01L21/8234;H01L29/66;H01L21/311;H01L21/306;H01L21/308 主分类号 H01L21/8234
代理机构 代理人
主权项 1. A method of fabricating a semiconductor device, comprising: forming active patterns that protrude upward from a top surface of a substrate; and forming a gate structure that crosses the active patterns, wherein forming the active patterns comprises: sequentially forming an underlying layer and a mask layer on the substrate, the mask layer comprising a first mask layer on the underlying layer and a second mask layer between the underlying layer and the first mask layer, forming a pair of sacrificial patterns on the mask layer; forming first spacers and a connection spacer, the first spacers spaced apart from each other with the pair of the sacrificial patterns interposed therebetween, the first spacers covering respective outer side surfaces of the sacrificial patterns, the connection spacer filling a space between the pair of the sacrificial patterns; etching the first mask layer using the first spacers and the connection spacer as an etch mask to form first mask patterns; forming second spacers to cover side surfaces of each of the first mask patterns; etching the second mask layer using the second spacers as an etch mask to form second mask patterns; etching the underlying layer using the second mask patterns as an etch mask to form lower mask patterns; and etching an upper portion of the substrate using the lower mask patterns as an etch mask.
地址 Suwon-si KR